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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
FEATURES
* 3 differential 2.5V, 3.3V LVPECL / ECL output * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Input frequency: 3.5GHz * Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V * -40C to 85C ambient operating temperature * Pin compatible with MC100LVEP34
GENERAL DESCRIPTION
The ICS873034 is a low skew, high performance Differential-to-2.5V, 3.3V LVPECL/ECL HiPerClockSTM Clock Generator a n d a m e m b e r o f t h e HiPerClockS TM family of High Perfor mance Clock Solutions from ICS. The ICS873034 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS873034 ideal for those clock distribution applications demanding well defined perfor mance and repeatability.
ICS
BLOCK DIAGRAM
nEN D Q LE PCLK nPCLK
/4 R
/8 R
PIN ASSIGNMENT
/2 R
Q0 nQ0
Q1 nQ1
Q0 nQ0 VCC Q1 nQ1 VCC Q2 nQ2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC nEN nc PCLK nPCLK VBB MR VEE
V BB
Q2 nQ2
ICS873034
16-Lead SOIC, 300MIL 7.5mm x 10.3mm x 2.3mm package body M Package Top View
MR
ICS873034
16-Lead TSSOP 4.4mm x 3.0mm x 0.92mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 873034AM www.icst.com/products/hiperclocks.html REV. A AUGUST 30, 2004
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
Type Description Differential output pair. LVPECL interface levels. Power supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Bias voltage. Pullup/ Clock input. Defaults to VCC/2 (.66) when left open. LVPECL interface levels. Pulldown Pulldown Clock input. Default LOW when left floating. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 6, 16 4, 5 7, 8 9 10 11 12 13 14 Name Q0, nQ0 VCC Q1, nQ1 Q2, nQ2 VEE MR VBB nPCLK PCLK nc Power Output Output Power Input Output Input Input Unused Output
No connect. Synchronizing clock enable. When LOW, clock outputs follow clock input. 15 nEN Input Pulldown When HIGH, Q outputs are forced LOW, nQ outputs are forced HIGH. LVTTL / LVCMOS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RPULLDOWN Parameter Input Pulldown Resistor Input Pullup Resistor Test Conditions Minimum Typical 75 37.5 Maximum Units K K
TABLE 3. TRUTH TABLE
Inputs PCLK Z ZZ nEN L H MR L L Function Divide Hold Q0:Q2 Reset Q0:Q2
X X H Z = LOW to HIGH transistion ZZ = HIGH to LOW transistion
873034AM
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 90C/W (0 lfpm) 89C/W (0 lfpm) cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA Package Thermal Impedance, JA
Operating Temperature Range, TA -40C to +85C
(Junction-to-Ambient) for 16 Lead SOIC (Junction-to-Ambient) for 16 Lead TSSOP
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 40 Maximum 3.8 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-ended) Input Low Voltage (Single-ended) Output Voltage Reference
2.075 1.43 1.86
-40C Min Typ
2.275 1.545 2.36 1.765 1.98 2.075 1.43 1.86
25C Max Min Typ
2.295 1.52 2.36 1.765 1.98 2.075 1.43 1.86
85C Max Min Typ
2.33 1.535 2.36 1.765 1.98 800
Max
Units
V V V V V V V
800 800 Peak-to-Peak Input Voltage Input High Voltage VCMR Common Mode Range; NOTE 2, 3 Input 150 150 PCLK, nPCLK IIH High Current Input -10 -10 -10 PCLK, nPCLK IIL Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
150
A A
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
-40C Min Typ
1.475 0.745 1.275 0.63 1.56 0.965 1.275 0.63
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage (Single-Ended) Input Low Voltage (Single-Ended) 25C Max Min Typ
1.495 0.72 1.56 0.965 1.275 0.63 800
85C Max Min Typ
1.53 0.735 1.56 0.965
Max
Units
V V V V
800 800 Peak-to-Peak Input Voltage Input High Voltage 1.2 1.2 1.2 VCMR Common Mode Range; NOTE 2, 3 Input 150 150 PCLK, nPCLK IIH High Current Input -10 -10 -10 PCLK, nPCLK IIL Low Current Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
mV
V 150 A A
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
Symbol VOH Parameter -40C Min Typ Max Min 25C Typ Max Min 85C Typ
-1.005 -1.765 800 0
Max
Units
V V V V
Output High Voltage; -1.025 -1.005 NOTE 1 Output Low Voltage; -1.755 -1.78 VOL NOTE 1 800 800 VPP Peak-to-Peak Input Voltage Input High Voltage VEE+1.2V 0 VEE+1.2V 0 VEE+1.2V VCMR Common Mode Range; NOTE 2, 3 Input PCLK, 150 150 IIH High Current nPCLK Input PCLK, -10 -10 -10 IIL Low Current nPCLK NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
150
A A
873034AM
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
OR
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
Symbol fMAX Parameter Input Frequency Propagation Delay; NOTE 1 Set/Reset Recover y Setup Time Hold Time Output Rise/Fall Time nEN nEN 20% to 80% -40C Min Typ 3.5 530 320 50 100 170
VCC = 2.375V TO 3.8V; VEE = 0V
25C 85C Max Min Typ 3.5 610 320 50 100 200 50 Max Units GHz ps ps ps ps ps %
Max
Min
Typ 3.5 560 320 50 100 180
t PD
tRR tS tH tR/tF
odc Output Duty Cycle 50 50 All parameters are measured at f 1GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Qx
SCOPE
VCC
VCC
LVPECL
nQx
nPCLK PCLK
V
PP
Cross Points
V
CMR
VEE
V EE
-0.375V to -1.8V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK PCLK
nPCLK PCLK
nEN
t HOLD t SET-UP
nQ0:nQ2 Q0:Q2
tPD
SETUP
AND
HOLD TIME
PROPAGATION DELAY
nQ0:nQ2 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q0:Q2
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
873034AM
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to
the negative input. The C1 capacitor should be located as close as possible to the input pin.
VCC
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference
voltage level VBB generated from the device is connected to the negative input.
VCC
C1 0.1u
CLK_IN
PCLK VBB nPCLK
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
125
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
VCC=2.5V
2.5V
VCC=2.5V
R1 250
Zo = 50 Ohm
R3 250
Zo = 50 Ohm
+
+
Zo = 50 Ohm
2,5V LVPECL Driv er
Zo = 50 Ohm
2,5V LVPECL Driv er
R1 50
R2 50
R2 62.5
R4 62.5
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL Driv er
R1 50
R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V
3.3V
3.3V
R1 50
R2 50
PCLK
3.3V Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
nPCLK
HiPerClockS PCLK/nPCLK
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3 125
R4 125
PCLK
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
C1
PCLK
Zo = 50 Ohm
C2
VBB nPCLK
Zo = 50 Ohm
nPCLK
LVPECL
R1 84
R2 84
HiPerClockS Input
PC L K/n PC LK
R5 100 - 200
R6 100 - 200
R1 50
R2 50
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK R4 120
3.3V
Zo = 50 Ohm
LVDS
C1
PCLK
R5 100
C2
VBB nPCLK
Zo = 50 Ohm
HiPerClockS PCLK/nPCLK
PC L K /n PC L K
R1 1K
R2 1K
R1 120
R2 120
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 5F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
For the LVPECL output drivers, only two terminations examples are shown in this schematic. More termination approaches are shown in the LVPECL Termination Application Note.
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of ICS873034 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver.
3.3V
3.3V
U1
9 10 11 12 13 14 15 16
R1 133
nQ2 Q2 VCC nQ1 Q1 VCC nQ0 Q0
8 7 6 5 4 3 2 1
R3 133
+
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
VEE MR VBB nCLK CLK nc nEN VCC
Zo = 50 Ohm
Zo = 50 Ohm
-
R2 82.5
R4 82.5
LVPECL
R9 50
R8 50
ICS873034
R10 50
Zo = 50 Ohm
+
Zo = 50 Ohm
-
(U1-3)
3.3V
(U1-6)
(U1-16)
R5 50
R6 50
C1 0.1uF
C2 0.1uF
C3 0.1uF
Optional Y-Termination
R7 50
FIGURE 6. ICS873034 APPLICATION SCHEMATIC EXAMPLE
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REV. A AUGUST 30, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS873034. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS873034 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 40mA = 152mW Power (outputs)MAX = 27.83mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 27.83mW = 83.5mW
Total Power_MAX (3.8, with all outputs switching) = 152mW + 83.5mW = 235.5mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 82C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.236W * 82C/W = 104.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA FOR 16-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 90C/W
200
82C/W
500
78C/W
TABLE 6B. THERMAL RESISTANCE JA FOR 16-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.005V
-V
OH_MAX
) = 1.005 =V - 1.78V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.78V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1.005V)/50] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.78V)/50] * 1.78V = 7.83mW Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
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REV. A AUGUST 30, 2004
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ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE FOR 16 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 90C/W
200
82C/W
500
78C/W
TABLE 7B. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS873034 is: 280
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REV. A AUGUST 30, 2004
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Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX
FOR
PACKAGE OUTLINE - M SUFFIX FOR 16 LEAD SOIC
16 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 10.10 7.4 0 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 16 2.65 -2.55 0.51 0.32 10.50 7.60 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MS-012
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REV. A AUGUST 30, 2004
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Integrated Circuit Systems, Inc.
ICS873034
LOW SKEW, /2, /4, /8 DIFFERENTIAL-TO2.5V, 3.3V LVPECL/ECL CLOCK GENERATOR
Package 16 Lead SOIC 16 Lead SOIC on Tape and Reel 16 Lead TSSOP 16 Lead TSSOP on Tape and Reel Count 46 per tube 1000 94 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS873034AM ICS873034AMT ICS873034AG ICS873034AGT Marking ICS873034AM ICS873034AM ICS873034AG ICS873034AG
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 873034AM
www.icst.com/products/hiperclocks.html
16
REV. A AUGUST 30, 2004

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